G14/G14X Verilog BCH ECC IP
The G14 and G14X families of IP are optimized around a 1KB correction block typically used with NAND devices using 8KB page sizes. The primary difference is the maximum number of errors supported:
The G14 was designed to support MLC flash as it transitioned to 1024B correction blocks. While still applicable for the MLC market, the G14 can also be used to future-proof SLC flash controllers since it supports both 512B and 1024B correction blocks. SLC flash requiring ECC4 or ECC8 over 512B blocks can also be managed with 1024B correction blocks to provide extended wear leveling and ensure that ECC requirements will be satisfied for several generations of SLC flash.
By integrating Cyclic Design's G14 ECC IP, your existing controller hardware and software can be easily extended to support higher levels of ECC with far less investment than developing ECC expertise in-house. Cyclic Design provides the G14 in an off-the-shelf configuration that fits well into most controller architectures or the IP can be customized to match your specific controller's requirements. Cyclic Design can also work with your engineers to address specific latency, bandwidth, or area requirements to provide an optimal ECC solution for your application.
- Optimized for 1024B correction blocks
- Dynamically variable block sizes (2-1800 bytes)
- Parametrized design to support numerous performance/area tradeoffs
- Area can be optimized by specifying a maximum ECC level via parameter
- Supports both single-channel and multiple channel configurations
- ECC IP delivered as Verilog Source with SystemVerilog Assertions